The present invention relates to a semiconductor device having a field effect transistor such as a MOSFET or MISFET and a method of manufacturing the same and, more particularly, to a semiconductor device having an E (Enhancement) type or D (Depletion) type transistor and an I (Intrinsic) type transistor, and a method of manufacturing the same.
In the field of semiconductors, market demands for higher element densities within chips and low-cost LSIs (semiconductor devices) are still present even at present. Particularly, in semiconductor memories such as nonvolatile memories, an increase in memory capacity and a decrease in chip size by increasing the element density, and a reduction in manufacturing cost by simplifying the process are urgent subjects.
Conventional measures to decrease the chip size will be described by exemplifying a nonvolatile memory.
In a nonvolatile memory, a high voltage is used in a data write and erase. This high voltage is generally obtained by boosting an external power supply voltage using a booster circuit based on a charge pumping technique within an LSI (reference 1: xe2x80x9cDesign for CMOS VLSIxe2x80x9d, edited by Iizuka, Baifuukan, pp. 192-193).
The booster circuit must be constituted by a large-capacity capacitor element because it must generate a very high voltage. Increasing the capacity of the capacitor element generally means to increase the capacitor area, i.e., the capacitor element itself. Accordingly, the occupied area of the booster circuit on the chip increases, resulting in a large chip size and high cost.
To solve this problem, in the nonvolatile memory, the boosting efficiency is conventionally increased by constituting the booster circuit by a MOSFET having a threshold voltage as low as about 0.1V and a small back-gate bias effect, (which is to be referred to as an I (Intrinsic) type MOSFET).
An I type n-channel MOSFET can be formed on a p-type silicon substrate having an impurity concentration of about 2xc3x971016 cmxe2x88x923 because no threshold voltage control impurity is implanted in an element area (channel portion of the MOSFET) (reference 2: S. M. Sze, xe2x80x9cSemiconductor Devicexe2x80x9d, translated by Nanjitsu, Kawabe, and Hasegawa, Sangyotosho, pp. 220-221).
That is, since no threshold voltage control impurity is implanted in the channel portion, the I type MOSFET is different from a general E type MOSFET in which a threshold voltage control impurity is implanted in a channel portion. In addition, the I type MOSFET has a smaller back-gate bias effect than that of the E type MOSFET (reference 3: xe2x80x9cFoundation of MOS Integrated Circuitxe2x80x9d, edited by Takeishi and Hara, Kindaikagakusha, pp. 12-13).
In this manner, constituting the booster circuit based on the charge pumping technique by the I type MOSFET contributes to a decrease in chip size because an increase in capacity of the capacitor element can be suppressed as low as possible in generating a high voltage.
In the field of semiconductors, the manufacturing cost must be reduced by simplifying the process (decreasing the number of steps) in order to achieve low-cost LSIs. Some conventional manufacturing methods will be described.
FIG. 33 is a sectional view of a semiconductor device formed by the first example of a conventional manufacturing process. FIG. 34 is a flow chart briefly showing the main steps of this manufacturing process.
As shown in FIG. 33, this semiconductor device comprises an E type or D type n-channel MOSFET 110a formed using a p-type well layer 115 in a p-type silicon substrate 111, and an I type MOSFET 110b formed using the ground of the p-type silicon substrate 111. Each element is surrounded by grating-like field oxide films, i.e., element isolation films 119. A p-type channel stopper diffusion layer 120 is formed immediately below each element isolation film 119.
In the first example of the manufacturing process, a PEP (PhotoEtching Process), ion implantation, and thermal diffusion are performed in step S11 to form the p-type well layer 115. In step S12, a PEP, ion implantation, and LOCOS oxidation are performed to form the element isolation films 119 and the p-type channel stopper diffusion layers 120. In step S13, a PEP and ion implantation are performed to implant an impurity for controlling the threshold voltage of the MOSFET 110a. In step S14, formation of the gate electrode and self-alignment ion implantation are performed to implant an impurity for forming source and drain layers. In step 515, the impurity is activated by annealing to complete the source and drain layers.
This manufacturing process is characterized by the well diffusion process and the three PEPs. That is, since the well diffusion process is a long-time thermal diffusion process, ion implantation for the well layer 115 and ion implantation for threshold voltage control or a channel stopper cannot be simultaneously performed.
FIG. 35 is a sectional view of a semiconductor device formed by the second example of the conventional manufacturing process. FIG. 36 is a flow chart briefly showing the main steps of this manufacturing process. The same reference numerals as in FIG. 33 denote the same parts of the sectional structure in FIG. 35, and a description thereof will be omitted.
In the second example of the manufacturing process, a PEP and LOCOS oxidation are performed in step S21 to form element isolation films 119. In step S22, a PEP and ion implantation are performed to implant an impurity for forming p-type channel stopper diffusion layers 120. In step S23, a PEP and ion implantation are performed to implant an impurity for controlling the threshold voltage of a MOSFET 110a and an impurity for forming a p-type well layer 115. In step S24, formation of a gate electrode and self-alignment ion implantation are performed to implant an impurity for forming source and drain layers. In step 525, the impurities are activated by annealing to complete the well layer 115, the channel stopper diffusion layers 120, and the source and drain layers.
FIGS. 37 to 42 are views sequentially showing the third example of the conventional manufacturing process as an improvement of the second example. FIG. 43 is a flow chart briefly showing the main steps of this manufacturing process.
In the third example of the manufacturing process, as shown in FIGS. 37 and 38, a silicon oxide film 112 is formed on a p-type silicon substrate 111 by, e.g., thermal oxidation. A silicon nitride film 116 is formed on the silicon oxide film 112 by, e.g., LPCVD.
A resist pattern 117 is formed on the silicon nitride film 116 by a PEP (PhotoEtching Process). Using the resist pattern 117 as a mask, the silicon nitride film 116 is patterned by RIE (Reactive Ion Etching).
Using the resist pattern 117 as a mask, a p-type impurity (e.g., boron ions) 118 is ion-implanted in the silicon substrate 111. Then, the resist pattern 117 is removed.
As shown in FIG. 39, LOCOS oxidation is performed using the silicon nitride film 116 as a mask to form field oxide films 119 having a film thickness of about 500 nm on the silicon substrate 111. At the same time, p-type diffusion layers (channel stoppers) 120 are formed immediately below the field oxide films 119. Thereafter, the silicon nitride film 116 is removed.
As shown in FIGS. 40 and 41, a resist pattern 121 is formed on the silicon oxide films 112 and the field oxide films 119 by a PEP. The resist pattern 121 has an opening above an element area where a general E type MOSFET is to be formed, and covers an element area where an I type MOSFET is to be formed.
Using the resist pattern 121 as a mask, a p-type impurity (e.g., boron ions) 128 is implanted to a deep portion in the silicon substrate 111 by high-energy ion implantation using a plurality of different acceleration energies of, e.g., about 400 keV and 300 keV.
Using the resist pattern 121 as a mask, a p-type impurity (e.g., boron ions) 129 for controlling the threshold voltage of the MOSFET is ion-implanted in the silicon substrate 111 using a low acceleration energy of about 40 keV. After that, the resist pattern 121 and the silicon oxide films 112 are removed.
As shown in FIG. 42, gate oxide films 123 are formed in the element areas surrounded by the field oxide films 119 by, e.g., thermal oxidation. Gate electrodes 124 are formed on the gate oxide films 123. Using the gate electrodes 124 as a mask, an n-type impurity (e.g., phosphorus) is implanted in the silicon substrate 111 by self alignment.
Silicon oxide films 130 are formed on the surfaces of the gate electrodes 124 by thermal oxidation. At the same time, the impurities in the silicon substrate 111 are activated to form a p-type well layer 115 and source and drain layers 125.
In short, as shown in FIG. 43, in the third example of the manufacturing process, a PEP, ion implantation, and LOCOS oxidation are performed in step S31 to form the element isolation films 119 and the p-type channel stopper diffusion layers 120. In step S32, a PEP and ion implantation are performed to implant an impurity for controlling the threshold voltage of the MOSFET 110a and an impurity for forming the p-type well layer 115. In step S33, formation of the gate electrodes 124 and self-alignment ion implantation are performed to implant an impurity for forming the source and drain layers 125. In step S34, the impurities are activated by annealing to complete the well layer 115 and the source and drain layers 125.
The feature of second and third examples of the manufacturing process is to implant an impurity to a deep portion in the silicon substrate using a high acceleration energy, and form the well layer 115 by activating the impurity. This manufacturing process does not require any long-time well diffusion process, and can contribute to a reduction in manufacturing cost owing to a short manufacturing time. In addition, this manufacturing process can also contribute to a reduction in cost by decreasing the number of PEPs because ion implantation for controlling the threshold voltage of the MOSFET 110a and ion implantation for forming the well layer 115 can be executed using the same mask.
According to the third example of the manufacturing process, the number of PEPs can be further decreased by one as a whole because the mask pattern (resist pattern 117) used in ion implantation for forming the p-type diffusion layers (channel stoppers) 120, and the pattern of the mask (silicon nitride film 116) used to form the field oxide films 119 are the same.
As described above, in the field of semiconductors, the market demands for a decrease in chip size by increasing the element density within the chip, and a reduction in manufacturing cost by simplifying the manufacturing process still remain. For example, in the nonvolatile memory, the booster circuit is constituted by the I type MOSFET in order to decrease the area of the booster circuit on the chip and reduce the chip size. The number of PEPs is decreased by using high-energy ion implantation in order to reduce the manufacturing cost by simplifying the manufacturing process.
However, if the manufacturing process of an LSI (semiconductor device) having both an E type MOSFET and an I type MOSFET is directly applied to an LSI not having any I type MOSFET, the process may become wasteful. Development of a technique which can be applied to all LSIs having MOSFETs and can simultaneously achieve a decrease in chip size by increasing the element density within the chip, and a reduction in manufacturing cost by simplifying the manufacturing process is desired.
It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same in which a decrease in chip size and a reduction in manufacturing cost can be simultaneously achieved.
According to a first aspect of the present invention, there is provided a semiconductor device comprising:
a semiconductor substrate of a first conductivity type having a common surface and a ground with a first resistivity;
a well layer of a first conductivity type formed in the common surface and having a second resistivity lower than the first resistivity, the well layer having a first portion for defining a first element area with the second resistivity, which consists essentially of part of the well layer, and a second portion for surrounding part of the substrate and defining a second element area with the first resistivity, which consists essentially of the ground; and
first and second transistors formed of field effect transistors with channels of a second conductivity type which are respectively arranged in the first and second element areas, each of the first and second transistors having source and drain layers of the second conductivity type which interpose a channel region in a channel-length direction, and a gate electrode facing the channel region via a gate insulating film.
According to a second aspect of the present invention, there is provided a method of manufacturing the semiconductor device of the first aspect,
the device further comprising an isolation layer consisting essentially of an insulator arranged in the common surface to surround the second element area, the second portion of the well layer being formed immediately below the isolation layer,
the method comprising the steps of:
forming the isolation layer in the common surface;
forming a first mask to cover a portion of the common surface corresponding to the second element area and have an opening at portions of the common surface corresponding to the first element area and the isolation layer;
simultaneously ion-implanting, using the first mask, a first carrier impurity of the first conductivity type in a portion of the common surface corresponding to the first element area and immediately below the isolation layer;
forming the gate insulating films on the common surface;
forming the gate electrodes in the first and second element areas;
simultaneously ion-implanting, using the gate electrodes as a mask, a second carrier impurity of the second conductivity type-in portions of the common surface corresponding to the source and drain layers of the first and second transistors; and
activating the first and second carrier impurities by annealing to simultaneously form the well layer, the source and drain layers of the first and second transistors.
According to a third aspect of the present invention, there is provided a semiconductor device comprising:
a semiconductor substrate of a first conductivity type having a common surface and a ground with a first resistivity;
first and second isolation layers consisting essentially of insulators formed in the common surface, the first and second isolation layers surrounding part of the substrate and respectively defining first and second element areas with the first resistivity, which consist essentially of the ground;
first and second transistors formed of field effect transistors with channels of a second conductivity type which are respectively arranged in the first and second element areas, each of the first and second transistors having source and drain layers of the second conductivity type which interpose a channel region in a channel-length direction, and a gate electrode facing the channel region via a gate insulating film; and
an intervening diffusion layer of the first conductivity type formed in the common surface to separate the first and second isolation layers, and having a second resistivity lower than the first resistivity.
According to a fourth aspect of the present invention, there is provided a method of manufacturing the semiconductor device of the third aspect,
the device further comprising
a well layer of the second conductivity type formed in the common surface to define a third element area, and
a third transistor formed of a field effect transistor with a channel of the first conductivity type which is arranged in the third element area, the third transistor having source and drain layers of the first conductivity type which interpose a channel region in the channel-length direction, and a gate electrode facing the channel region of the third transistor via a gate insulating film,
the method comprising the steps of:
forming the isolation layers in the common surface;
forming a first mask to cover portions of the common surface corresponding to the first and second element areas, and have an opening at a portion of the common surface corresponding to the third element area;
ion-implanting, using the first mask, a first carrier impurity of the second conductivity type in the portion of the common surface corresponding to the third element area;
forming the gate insulating films on the common surface;
respectively forming the gate electrodes in the first to third element areas;
forming a second mask to cover portions of the common surface corresponding to the third element area and the intervening diffusion layer, and have openings at portions of the common surface corresponding to the first and second element areas;
simultaneously ion-implanting a second carrier impurity of the second conductivity type in portions of the common surface corresponding to the source and drain layers of the first and second transistors, by using the second mask and the gate electrodes in the first and second element areas as a mask;
forming a third mask to cover portions of the common surface corresponding to the first and second element areas, and have an opening at portions of the common surface corresponding to the third element area and the intervening diffusion layer;
simultaneously ion-implanting a third carrier impurity of the first conductivity type in portions of the common surface corresponding to the source and drain layers of the third transistor and the intervening diffusion layer, by using the third mask and the gate electrode in the third element area as a mask; and
activating the first to third carrier impurities by annealing to simultaneously form the well layer, the source and drain layers of the first to third transistors, and the intervening diffusion layer.
Note that, the term, a carrier impurity, means an impurity for providing a semiconductor layer with carriers, and materials simply referred to as an impurity hereinafter all denote a carrier impurity. Further, in addition to MOSFETS, the present invention may be similarly applied to MISFETs which employ a gate insulating film formed of an insulating film other than an oxide film. Furthermore, the present invention is similarly applied to P-channel and N-channel structures, and in particular, is effective for a semiconductor device having a CMOS structure.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.